Fast Fourier Transform Vitis High Level Synthesis Implementation
Features of the lesson
➢ FFT IP core microarchitecture for Vitis HLS 2022.2 and Python modeling for verification
➢ HLS FFT IP core Implementation, Co-simulation and performance analysis
➢ Vivado 2022.2 Hardware Design with HLS FFT IP core, AXI DMA and Zynq 7000 Processing System
➢ C Standalone Application with C-drivers for AXI DMA
➢ Bring-up the Hardware Design with HLS FFT IP core on Arty Z7-20 board and verification in Python
Fully pipelined, axi stream compliant
Fast Fourier Transform IP core implementation in Vitis HLS
Matched Filter Vitis High Level Synthesis Implementation
Fully pipelined, run time configurable, axi stream / lite compliant
Matched Filter IP core
implementation in Vitis HLS
Features of the lesson
➢ Matched Filter in frequency domain IP core microarchitecture for Vitis HLS 2022.2 and Python modeling for verification
➢ HLS MF IP core Implementation, Co-simulation and performance analysis
➢ Vivado 2022.2 Hardware Design with HLS MF IP core, Scatter-Gather AXI DMA and Zynq 7000 Processing System
➢ C Standalone Application with C-drivers and Run Time Configuration for HLS MF IP core and Scatter-Gather AXI DMA
➢ Bring-up the Hardware Design with HLS MF IP core on Arty Z7-20 board with verification in Python
Cell-Averaging CFAR Vitis High Level Synthesis Implementation
Fully pipelined, run time configurable, axi stream / lite compliant
Cell-Averaging CFAR IP core
implementation in Vitis HLS
Features of the lesson
➢ Cell-Averaging Constant False Alarm Rate (CFAR) IP core microarchitecture for Vitis HLS 2022.2 and Python modeling for verification
➢ HLS CACFAR IP core Implementation, Co-simulation and performance analysis
➢ Vivado 2022.2 Hardware Design with HLS CACFAR IP core, AXI DMA and Zynq 7000 Processing System
➢ C Standalone Application with C-drivers and Run Time Configuration for HLS CACFAR IP core and AXI DMA
➢ Bring-up the Hardware Design with HLS CACFAR IP core on Arty Z7-20 board with verification in Python