AXI DMA with HLS — Source Code Package

This package provides complete, production-ready source code for implementing high-performance PS–PL data transfer on Zynq-7000 and Zynq UltraScale+ SoCs using Vitis High-Level Synthesis (HLS).

What this package includes

Hardware (Programmable Logic)

• HLS-based AXI DMA TX and RX IP cores

• AXI Memory-Mapped and AXI-Stream interfaces

• DDR ↔ PL data transfer architecture

• Vivado/Vitis HLS project structure

Software (Processing System)

• AXI DMA C drivers for:

  • Standalone (Cortex-R5)

  • Embedded Linux (Cortex-A53)

• Linux user-space examples:

  • C application

  • Python application

• UIO-based driver model (/dev/uioX, sysfs)

• Read/write/mmap/ioctl usage examples

Python Interface

• SWIG-based wrapper

• Generated Python module (_axidma.so)

• High-level Python API (axidma.py)

• Example Python user application

System integration examples

• Embedded Linux deployment (Buildroot)

• Device tree and FPGA Manager usage

• OpenAMP example for Cortex-R5

• Multi-processor (A53 + R5) interaction overview