This package provides a complete, hardware-oriented implementation of Constant False Alarm Rate (CFAR) detectors for radar signal processing, implemented using Vitis High-Level Synthesis (HLS) and integrated into a Zynq-based embedded Linux system.
The accompanying video lessons are freely available on YouTube.
This product contains all source code used in the lessons, including HLS IP cores, software drivers, and simulation scripts.
Fully pipelined CFAR HLS IP cores
Cell-Averaging CFAR (CA-CFAR)
Ordered-Statistic CFAR (OS-CFAR)
AXI-Stream interfaces (S-AXIS / M-AXIS)
Run-time configurable parameters
Fixed-point signal modeling and performance evaluation
Complex input signal simulation
CFAR thresholding and detection analysis
Verification of detection performance vs noise floor
Vivado hardware design
Integration of CFAR IP cores
AXI Stream Switch and AXI DMA
Tested hardware design for Arty Z7-20
Embedded Linux support
Buildroot out-of-tree configuration
Linux deployment for Zynq-7000 SoCs
Dynamic FPGA reconfiguration support
Software and automation
Linux C applications for CFAR control and data transfer
AXI DMA and AXI Stream Switch handling
TCL scripts for Vivado automation
SDK support for application development
This package provides a complete, hardware-oriented implementation of Constant False Alarm Rate (CFAR) detectors for radar signal processing, implemented using Vitis High-Level Synthesis (HLS) and integrated into a Zynq-based embedded Linux system.
The accompanying video lessons are freely available on YouTube.
This product contains all source code used in the lessons, including HLS IP cores, software drivers, and simulation scripts.
Fully pipelined CFAR HLS IP cores
Cell-Averaging CFAR (CA-CFAR)
Ordered-Statistic CFAR (OS-CFAR)
AXI-Stream interfaces (S-AXIS / M-AXIS)
Run-time configurable parameters
Fixed-point signal modeling and performance evaluation
Complex input signal simulation
CFAR thresholding and detection analysis
Verification of detection performance vs noise floor
Vivado hardware design
Integration of CFAR IP cores
AXI Stream Switch and AXI DMA
Tested hardware design for Arty Z7-20
Embedded Linux support
Buildroot out-of-tree configuration
Linux deployment for Zynq-7000 SoCs
Dynamic FPGA reconfiguration support
Software and automation
Linux C applications for CFAR control and data transfer
AXI DMA and AXI Stream Switch handling
TCL scripts for Vivado automation
SDK support for application development
