This package provides a complete, hardware-oriented implementation of a radar matched filter for Zynq-based FPGA systems, implemented using Vitis High-Level Synthesis (HLS).
Both time-domain and frequency-domain matched filter architectures are included, allowing direct comparison of performance, latency, and resource utilization.
The accompanying video lessons are freely available on YouTube. This product contains all source code used in the lessons, including HLS IP cores, hardware design files, Linux software, and performance evaluation scripts.
Included in this source code package:
• Fully pipelined matched filter IP cores implemented in Vitis HLS
• Time-domain and frequency-domain matched filter architectures
• Integration with AXI DMA and AXI Stream Switch IP cores
• Performance comparison of time vs frequency domain implementations
• Vivado hardware design for Zynq-7000 SoCs
• Buildroot-based Embedded Linux deployment
• Linux C API for run-time configuration and data transfer
• Tested on Arty Z7-20
This package provides a complete, hardware-oriented implementation of a radar matched filter for Zynq-based FPGA systems, implemented using Vitis High-Level Synthesis (HLS).
Both time-domain and frequency-domain matched filter architectures are included, allowing direct comparison of performance, latency, and resource utilization.
The accompanying video lessons are freely available on YouTube. This product contains all source code used in the lessons, including HLS IP cores, hardware design files, Linux software, and performance evaluation scripts.
Included in this source code package:
• Fully pipelined matched filter IP cores implemented in Vitis HLS
• Time-domain and frequency-domain matched filter architectures
• Integration with AXI DMA and AXI Stream Switch IP cores
• Performance comparison of time vs frequency domain implementations
• Vivado hardware design for Zynq-7000 SoCs
• Buildroot-based Embedded Linux deployment
• Linux C API for run-time configuration and data transfer
• Tested on Arty Z7-20
