Bartlett Beamformer FPGA IP Core
Hardware-accelerated Bartlett beamforming for Direction-of-Arrival estimation on AMD/Xilinx FPGAs.
EVALUATION
For functional evaluation and FPGA integration testing.
IP Core Features
1D ULA processing
Floating-point implementation
Full angular spectrum computation (512 directions)
Balanced resource/performance optimization
Python API/application
C application for Linux and bare-metal
Vivado integration example
Implementation Results
Zynq-7000, 100 MHz target clock
DSP slices: 18
LUTs: 8,796
FFs: 7,234
BRAM: 18
Latency: 33,295 cycles (~333 µs)
Initiation Interval: 33,296 cycles (~333 µs)
PRO
A reference implementation for commercial deployment, customizable to application-specific architecture and performance requirements.
IP Core Features
2D URA processing
Fixed-point implementation
Runtime-configurable Regions of Interest (ROIs)
128 × 128 angular grid
On-chip steering-vector generation
Balanced resource/performance optimization
IP-core runtime statistics
Python API/application
C application for Linux and bare-metal
Vivado integration example
Implementation Results
Zynq-7000, 100 MHz target clock
DSP slices: 13
LUTs: 12,924
FFs: 7,369
BRAM: 84
Latency: 162,332 cycles (~1.62 ms, maximum 16 × 16 ROI)
Initiation Interval: 162,333 cycles (~1.62 ms)
