Bartlett Beamformer FPGA IP Core
Hardware-accelerated Bartlett beamforming for Direction-of-Arrival estimation on AMD/Xilinx FPGAs.
EVALUATION
For functional evaluation and FPGA integration testing.
The evaluation core is verified against an independent Python floating-point reference using deterministic single- and two-source ULA scenarios with configurable per-source SNR. For each scenario, the same covariance matrix is processed by the Python model and the Vitis HLS implementation.
The upper plot compares the full normalized Bartlett angular spectrum from Python and HLS for a representative two-source case. The green dashed curve shows the point-by-point absolute spectrum error.
The lower plot summarizes the numerical agreement across all validation scenarios using the RMSE between the normalized Python and HLS spectra. Lower values indicate closer agreement.
IP Core Features
1D ULA processing
Floating-point implementation
Full angular spectrum computation (512 directions)
Balanced resource/performance optimization
Python API/application
C application for Linux and bare-metal
Vivado integration example
Implementation Results
XC7Z020-1CLG400C, 100 MHz target clock
DSP slices: 18 / 220 (8.2%)
LUTs: 8,796 / 53,200 (16.5%)
FFs: 7,234 / 106,400 (6.8%)
BRAM: 18 / 140 (12.9%)
Latency: 33,295 cycles (~333 µs)
Initiation Interval: 33,296 cycles (~333 µs)
PRO
A reference implementation for commercial deployment, customizable to application-specific architecture and performance requirements.
The Pro core is verified against an independent Python floating-point reference using deterministic 2D URA scenarios with up to two sources, configurable per-source SNR, and two runtime-configurable regions of interest.
The left plots show the HLS Bartlett response inside both ROIs for a representative two-source scenario, including the true source positions and HLS response peaks.
The right plot summarizes the numerical difference between the fixed-point HLS implementation and the floating-point Python reference using the RMSE over all evaluated samples in both ROIs.
IP Core Features
2D URA processing
Fixed-point implementation
Runtime-configurable Regions of Interest (ROIs)
128 × 128 angular grid
On-chip steering-vector generation
Balanced resource/performance optimization
IP-core runtime statistics
Python API/application
C application for Linux and bare-metal
Vivado integration example
Implementation Results
XC7Z020-1CLG400C, 100 MHz target clock
DSP slices: 13/ 220 (5.9%)
LUTs: 12,924 / 53,200 (24.3%)
FFs: 7,369 / 106,400 (6.9%)
BRAM: 84 / 140 (60.0%)
Latency: 162,332 cycles (~1.62 ms, maximum 16 × 16 ROI)
Initiation Interval: 162,333 cycles (~1.62 ms)
