This package provides a complete, hardware-oriented implementation of a Direct Digital Synthesizer (DDS) using Vitis High-Level Synthesis (HLS), including several DDS architectures, FPGA integration, embedded Linux support, and signal-quality evaluation tools.
The accompanying video lessons are freely available on YouTube.
This product contains all source code used in the lessons, including HLS IP cores, Vivado integration scripts, Linux software, and Python analysis tools.
Fully pipelined DDS HLS IP cores
Phase-truncated DDS
Dithered DDS
Taylor-series-corrected DDS
AXI4-Stream interfaces
Configurable phase accumulator / output parameters
DDS signal modeling and performance evaluation
Python signal-generation models
Spectral analysis
Spurious-Free Dynamic Range (SFDR) estimation
Comparison of DDS architectures
Vivado hardware design
Integration of DDS HLS IP cores
AXI Stream Switch
AXI DMA
Tested hardware design for Arty Z7-20
Embedded Linux support
Buildroot out-of-tree configuration
Linux deployment for Zynq-7000 SoCs
Dynamic FPGA configuration support
Software and automation
Linux C/C++ API
AXI DMA and AXI Stream Switch handling
Runtime DDS configuration
TCL scripts for Vivado automation
SDK/application development support
This package provides a complete, hardware-oriented implementation of a Direct Digital Synthesizer (DDS) using Vitis High-Level Synthesis (HLS), including several DDS architectures, FPGA integration, embedded Linux support, and signal-quality evaluation tools.
The accompanying video lessons are freely available on YouTube.
This product contains all source code used in the lessons, including HLS IP cores, Vivado integration scripts, Linux software, and Python analysis tools.
Fully pipelined DDS HLS IP cores
Phase-truncated DDS
Dithered DDS
Taylor-series-corrected DDS
AXI4-Stream interfaces
Configurable phase accumulator / output parameters
DDS signal modeling and performance evaluation
Python signal-generation models
Spectral analysis
Spurious-Free Dynamic Range (SFDR) estimation
Comparison of DDS architectures
Vivado hardware design
Integration of DDS HLS IP cores
AXI Stream Switch
AXI DMA
Tested hardware design for Arty Z7-20
Embedded Linux support
Buildroot out-of-tree configuration
Linux deployment for Zynq-7000 SoCs
Dynamic FPGA configuration support
Software and automation
Linux C/C++ API
AXI DMA and AXI Stream Switch handling
Runtime DDS configuration
TCL scripts for Vivado automation
SDK/application development support
